Fast modulo 2n+1 multi-operand adders and residue generators

In this manuscript novel architectures for modulo 2 þ 1 multi-operand addition and residue generation are introduced. The proposed arithmetic components consist of a translation stage, an inverted endaround-carry carry-save-adder tree and an enhanced diminished-1 modulo 2 þ 1 adder. Qualitative and quantitative results indicate that the proposed architectures result in significantly faster and in several cases smaller circuits than the previously proposed. & 2009 Elsevier B.V. All rights reserved.